Manuscript Title:

DESIGN OF LEVEL SHIFTER FOR LOW POWER APPLICATION

Author:

C.V. KRISHNA REDDY

DOI Number:

DOI:10.17605/OSF.IO/J25CF

Published : 2021-10-31

About the author(s)

1. C.V. KRISHNA REDDY - Nalla Narasimha Reddy Education Society Group of Institutions, Hyderabad.

Full Text : PDF

Abstract

Sub-edge spillage power is expanding as Vt scales and is relied upon to turn into a critical part of complete power utilization. Three novel designs of in 0.35-micrometer level shifters for low-power uses innovation are introduced in this work. The proposed circuits take advantage of the stacking technique's advantages of lower leakage current and reduced leakage power. Three NMOS transistors have been added to the conventional level shifter, resulting in a complete power utilization of 402.2264pW, contrasted with 0.49833nW with the current circuit. The alteration of a solitary stock level shifter with the expansion of two NMOS semiconductors brings about an all-out power utilization the difference is 108.641pW vs. 31.06nW. Another device uses 396.75pW of total power, a contention mitigated level shifter (CMLS) with three more transistors, compared to 0.4937354nW total power. Three proposed circuits demonstrate superior energy efficiency, albeit at the expense of a little latency. With regard to all of the circuit designs that have been floated, a 3.3V output level was obtained with a 1.6V input pulse.


Keywords

Power consumption, leakage current, transistors, shifter configuration, CMOS